Continued shrinkage of process geometries in complementary metal oxide semiconductor (CMOS) technologies and the like has led to improved manufacturing processes enabling the patterning of devices on integrated circuits. These devices, including for example interconnect lines and transistors (e.g., FinFET), may have geometric features with pitch patterning less than about 40 nanometers (nm). One technique used to achieve such geometric features is known as sidewall image transfer (SIT). In general, the SIT process includes patterning a sacrificial layer (known as a “mandrel”) on a silicon structure (e.g., silicon on insulator (SOI)), depositing a mask layer over the mandrel and silicon, etching back the mask layer to form sidewalls, and removing the mandrel and etching the silicon to form features or “fins.” The SIT process can achieve twice the pattern density over standard optical lithographic processing techniques by obtaining fins with sub-resolution line-widths, i.e., line-widths less than the critical dimension (CD) of a standard optical lithography process. With the continuous scaling of devices, methods for removing mandrels have proven to be challenging. Typically, a cut mask is used to identify the areas which will be removed by the etching process.